The present invention relates to vertical transistor fabrication. In particular, the present invention relates to fabrication of a trench with a curvilinear trench bottom for a vertical transistor. The present invention also relates to an application of the vertical transistor with a floating gate that follows the contour of the curvilinear trench bottom.
Integrated circuit technology relies on transistors to formulate functional circuits. The complexity of these circuits requires the use of an ever-increasing number of transistors. As the number of transistors increases, the surface space on the semiconductor substrate becomes more valuable.
Miniaturization is the process of crowding more active devices upon a given amount of semiconductor surface space, while improving both fabrication cost and device performance. As the surface space on a semiconductor substrate becomes more crowded with active devices, one solution to the crowding is to build a device that is in a vertical orientation to the semiconductor substrate.
Semiconductor processing of metal oxide semiconductor field-effect transistors (MOSFETs) requires the formation of a gate that will make an active device. The gate may typically be a conductor that is insulated from the semiconductor substrate by a dielectric layer such as a gate oxide layer over the semiconductor substrate. One particular MOSFET of interest is the vertical MOSFET because the gate is disposed vertically downward into the semiconductor substrate. As miniaturization progresses, the size and shape of the vertical transistor and the quality of the gate oxide layer become more important to both processing yield and to field use life.
Typically, a vertical transistor is formed in a rectilinear recess that includes two substantially vertical sidewalls and a substantially horizontal bottom. The recess is next covered with a dielectric layer. As such, the corner between sidewall and bottom may be substantially a right angle or there about, as the sidewalls are sometimes tapered outward from bottom to top of the recess. Because of the corner, there exists a greater likelihood of the dielectric layer breaking down at the corner because of enhanced electrical field activity at the corner. Consequently, the corner causes a reliability issue for the transistor as a field failure will result once the dielectric layer has broken down.
The above-mentioned problems with integrated circuits and other problems are addressed by embodiments set forth herein and will be understood by reading and studying the written description. Structure, process, and system embodiments are set forth herein.
In one embodiment, a vertical transistor is provided that is disposed in a recess that has more than three monolithic crystallographic surfaces. In the recess, the more than three monolithic crystallographic surfaces may be referred to as a whole as a substantially curvilinear profile or a curvilinear, segmented-surface profile. Processing includes conditions that cause the substantially right-angle, three-surface recess profile to reshape with an epitaxial film that causes the recess profile to deviate from the substantially right-angle, three-surface recess profile, toward forming a multiple-crystallographic surface, curvilinear recess profile.
In another embodiment, processing conditions include the use of hydrogen that may cause silicon or other semiconductive material to mobilize and redeposit to form the characteristic curvilinear recess profile.
In another embodiment, processing includes an anneal that is used to repair or smooth dangling semiconductor bonds that form the characteristic curvilinear recess profile. This process flow adds to both preferred tunneling and a more uniform gate oxide layer.
In another embodiment, the process is carried out on a  less than 100 greater than  monocrystalline silicon material and a metal oxide semiconductor field effect transistor is fabricated. The vertical transistor in each embodiment has the epitaxial semiconductor film. The epitaxial semiconductor film may have a minor thickness that is closer to the upper surface of the semiconductor substrate than to the former bottom of the recess, and a major thickness that is closer to the former bottom of the recess than the upper surface.
In another embodiment, an electrode is disposed in the recess, upon a gate oxide layer, and the electrode is processed to have an upper surface that is below the upper surface of the semiconductor substrate. This positioning of the electrode places it away from any sharp corners of the semiconductor substrate.
In another embodiment, the vertical transistor is fabricated between two shallow trench isolation structures, wherein the characteristic curvilinear profile of epitaxial semiconductor material forms on the semiconductive sidewalls, but polycrystalline material forms on the shallow trench isolation structures, if at all, to a lesser amount than the epitaxial semiconductor material.
In another embodiment, a minimum photolithographic feature comprises the width of the shallow trench isolation structure and the shallow trench isolation structure is disposed in a direction that is parallel with the gate from source to drain.
In another embodiment, the vertical transistor is part of an electrical device that includes the semiconductor substrate and a chip package. In another embodiment, the vertical transistor is part of an electrical device that includes the semiconductor substrate in a chip package and the chip package is part of a memory module. In another embodiment, the memory module is part of a dynamic random access memory module. In another embodiment, the vertical transistor is part of an electronic system. In another embodiment, the vertical transistor is fabricated with a floating gate. In another embodiment, the vertical transistor is fabricated with a floating gate that is part of a flash memory device.
These and other embodiments, aspects, advantages, and features of embodiments will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the embodiments and referenced drawings or by practice of embodiments.